1. Field of the Invention
The present invention relates to a latch clock generation circuit which outputs latch signals sequentially from multiple output terminals thereof in synchronization with a system clock, and a serial-parallel conversion circuit including the latch clock generation circuit.
2. Description of Related Art
Latch clock generation circuits which sequentially varies outputs from multiple output terminals thereof in synchronization with a system clock are today used in a variety of electrical circuits. For example, such latch clock generation circuits are often incorporated into a serial-parallel conversion circuit which simultaneously outputs, as parallel data, serial data received in time series. In such a serial-parallel conversion circuit, the latch clock generation circuit is used to generate a trigger signal to be sent to multiple latch circuits which hold data.
As shown in FIG. 7, a latch clock generation circuit 70 includes multiple latch signal generation circuits 72. The latch signal generation circuits 72 each receive a system clock signal GCLK and output a latch signal LCKn (n being 0 and a positive integer of one or more) in synchronization with the system clock signal.
As shown in FIG. 7, the latch signal generation circuit 72 includes a D-flip-flop (D-FF) 74 and an AND element 76. A control signal Xn−1 from the preceding stage or a line clock signal STP is input to an input terminal D of the D-FF 74. An inverse signal of a system clock signal GCLK is input to a clock terminal C. An output terminal Q of the D-FF 74 is connected to the AND element 76 and an input terminal D of a D-FF 74 included in a latch signal generation circuit 72 of the following stage. The system clock signal GCLK is also input to the AND element 76.
When the control signal Xn−1 supplied to the input terminal D of the D-FP 74 or the line clock signal STP is a high level, a control signal Xn of a high level is outputted from the output terminal Q of the D-FF 74 at a timing when the system clock signal GCLK becomes low level. Consequently, in the AND element 76, a latch signal LCKn is raised to high level when the system clock signal GCLK next becomes high level.
When the control signal Xn−1 or the line clock signal STP is a low level, a signal of a low level is output from the output terminal Q of the D-FF 74 at a timing when the system clock signal GCLK becomes low level. At this time, in the AND element 76, the latch signal LCKn becomes low level independently of the level of the system clock signal GCLK.
FIG. 8 shows a timing chart of the operation of the latch clock generation circuit 70. In FIG. 8, there is shown a timing chart for an example wherein four latch signal generation circuits 72 are provided. The line clock signal STP input to the latch clock generation circuit 70 of the first stage is generated by an external control section (not shown). The line clock signal STP has a period equal to or longer than a time period obtained by multiplying the period of the system clock signal GCLK by the number of the latch signal generation circuits 72. For example, when a number n of the latch signal generation circuits 72 are provided, the period of the line clock signal STP is equal to or longer than n times the period of the system clock signal GCLK. Here, the line clock signal STP has a period equal to the sum of a time period of four times the period A of the system clock signal GCLK and a waiting time T, i.e., a period of 4A+T. In one period, the line clock signal STP is made a high level during a time period corresponding to one clock by being in synchronization with the system clock signal GCLK. This line clock signal STP is input to the input terminal D of the D-FF 74 included in the latch signal generation circuits 72 of the first stage.
When the line clock signal STP becomes high level at time t0, and then the system clock signal GCLK falls to low level at time t1, a high level control signal X0 is output from the output terminal Q of the D-FF 74 of the first stage. When the system clock signal GCLK becomes a high level at time t2, a latch signal LCK0 of high level is output from the AND element 76 of the first stage. The D-FF 74 of the second stage receives the control signal X0 from the D-FF 74 of the first stage. Thus, when the system clock signal GCLK becomes low level at time t3, a control signal X1 of a high level is output from the output terminal Q of the D-FF 74 of the second stage. When the system clock signal GCLK becomes high level at time t4, a latch signal LCK1 of a high level is output from the AND element 76 of the second stage. Similarly, a control signal and latch signal are output from the latch signal generation circuit 72 of the third and fourth stages.
Accordingly, in one period of the line clock signal STP, high level latch signals LCK0, LCK1 . . . are sequentially output from the latch signal generation circuits 72 of the first stage to the final stage in synchronization with the system clock signal GCLK.
As shown in FIG. 7, a serial-parallel conversion circuit includes multiple flip-flop sets 90. Each of the flip-flop sets 90 includes a parallel circuit composed of the same number of D-FFs 92 as the number of bits of a serial transmission line Dn. For example, with a serial transmission line Dn of 18 bits Dn [0] to Dn [17], each of the flip-flop sets 90 includes eighteen D-FFs 92. Data Dn[0] to Dn[17] (data set Dn [0, 17]) transmitted in time series are input to terminals D of each of the D-FFs 92 included in the flip-flop set 90. A latch signal LCKn output from the latch generation circuit 72 of the n-th stage corresponding to each said flip-flop set 90 is input to a clock terminal C of the D-FF 92 included in the flip-flop set 90 of the n-th stage.
Consequently, whenever the latch signals LCK0, LCK1 . . . change to a high level, in order of from the first stage to the final stage, in synchronization with the system clock signal GCLK, data input at that time is held at each of the flip-flop sets 90.
When the serial data Dn [0, 17] are input in synchronization with the system clock signal GCLK, the data Dn [0, 17] can be sequentially held by each flip-flop set 90 and output in synchronization with the system clock signal GCLK. As such, serial data is converted to parallel data.
Also, there has been disclosed a serial-parallel conversion circuit in which data can be captured with a short period and the scales of circuits corresponding to the flip-flop set and latch clock generation circuit are reduced, whereby power consumption is lowered.
Also, there has been disclosed a serial-parallel conversion circuit in which the reduction of power consumption of a latch clock generation circuit is achieved by replacing D-FFs included in the latch clock generation circuit with simple gate circuits.
Further, there has been disclosed a latch signal generation circuit in which a system clock signal is received via a switch. By controlling the opening and closing of the switch, the system clock signal is selectively supplied only to a latch signal generation circuit of that stage which has reached a significant level, whereby the power consumption in the latch signal generation circuit can be reduced.
As described above, the conventional latch clock generation circuit 70 includes a large number of D-FFs 74 and operates in synchronization with the system clock signal GCLK. As the system clock signal GCLK is generally of a high frequency, these multiple latch clock generation circuits 70 consume a great amount of electrical power. Consequently, when a serial-parallel conversion circuit is applied to an LCD controller for a mobile telephone or a digital camera, the power consumption of the latch clock generation circuit can be problematic.